Is this truly possible? I thought you will have microcode in any (x86) instance unless you’re using Libreboot on an ancient Core Duo. Even then Leah will tell you, ‘while you can technically run without the microcode blob it will not run correctly’ even back then (IIRC).
As far as I understand it, the microcode was the hotfix for the expired original x86 patents, so pretty much universally required on all newer systems.
I’m no expert, but does the CPU scheduler work without microcode? How does the kernel determine the ISA available. I’m mostly curious because Intel 12th gen P-cores have a chance of including the more advanced enterprise server AVX instruction set. If any kernel does not require microcode, the scheduler must have a way to differentiate and manage running processes automatically so that a process with an AVX command is never interrupted and moved to the next available logical core where that core could be an E-core. That or there must be some scheme to create CPU set isolation and a way to determine if the more advanced AVX instructions are present. This would require an interesting way of handling spin up of idle cores, power management, and a complex way of handling thread interrupts.
I probably wouldn’t understand most of what I might find on such a system, but it would be fun to read about and try to grasp. I think such a think is likely in the future, perhaps we are already in that future. I largely live under a rock, so let me know if we are there yet.