EmbeddedEntropy , 8 months ago

I’ve written hundreds (thousands?) of GNU Makefiles over the past 30 years and never had a need to unconditionally run particular targets before all others. GNU Make utility is a rule-based language. I’d suggest what you’re attempting to do is enforce an imperative programming language model onto a rule-based programming language model, which you’re going to run into trouble trying to code in a different language model than the tool’s native model.

Can you provide what you mean by check the environment, and why you’d need to do that before anything else?

For example, in the past I’ve want to determine if and which particular command was installed, so I have near the top of my Makefile:

<span style="color:#323232;">container_command_defaults = podman docker
</span><span style="color:#323232;">container_command_default_paths := $(shell command -v $(container_command_defaults))
</span><span style="color:#323232;">
</span><span style="color:#323232;">ifndef container_command
</span><span style="color:#323232;">  container_command = $(firstword $(container_command_default_paths))
</span><span style="color:#323232;">  ifeq ($(container_command),)
</span><span style="color:#323232;">    $(error You must have docker or podman installed)
</span><span style="color:#323232;">  endif
</span><span style="color:#323232;">endif
</span>

Using the := operator with $(shell …) is a way to run a command while GNU Make is initially parsing your Makefile. Normally, using := assignment operator is antithetical to a rule-based language, so you want to limit its use as much as possible, but unusual exceptions can exist.

I’m also unclear what you mean by “ensure variables are set”. What kind of variables?

The above snippet shows how you can check if a makefile variable is set when the Makefile is first parsed, if not, declare an error and exit. (The same approach works for environment variables too.)

Preparing a particular layout ahead of time is not the best approach. I’d suggest a given layout is nothing more than dependencies that should be declared as such.

Also, running specific targets or rules unconditionally can lead to trouble later as your Makefile grows up. You may eventually have additional targets that say provide information about the build’s state or run checks or tests. You wouldn’t want those targets necessarily to go off and build an entire tree of directories for you or take other unnecessary actions.

If you want to ensure certain directories are present, add those as dependencies for those targets with the | character. For example:

<span style="color:#323232;">build_directory ?= build
</span><span style="color:#323232;">build_make = $(MAKE) ...
</span><span style="color:#323232;">targets = ...
</span><span style="color:#323232;">
</span><span style="color:#323232;">all: FORCE | $(build_directory)
</span><span style="color:#323232;">	$(build_make) $(targets)
</span><span style="color:#323232;">
</span><span style="color:#323232;">$(build_directory):
</span><span style="color:#323232;">	mkdir -p -- '$@'
</span>

Even though I’ve been writing GNU Makefiles for decades, I still am learning new stuff constantly, so if someone has better, different ways, I’m certainly up for studying them.